The present invention relates generally to electronic memory devices, and more particularly to non-volatile memory cells for use in electronic memory devices such as electrically erasable programmable read-only memories (EEPROMs).
A non-volatile memory device is capable of retaining stored information after disconnection of its power source. An EEPROM is a type of non-volatile memory device in which information is written to and erased from the memory cells thereof using an electrical signal. EEPROMs are often implemented as xe2x80x9cflashxe2x80x9d memory devices in which all memory cells or designated sectors of cells can be simultaneously erased. Such devices typically utilize floating gate transistor structures in which the floating gate used to store charge upon programming of the cell is formed from a single layer of polysilicon. These single-poly flash EEPROMs are particularly well suited for use in applications requiring embedded, low cost, medium density arrays of non-volatile memory cells, such as parameter, protocol, code and data storage for processors and other types of integrated circuits.
Examples of single-poly flash EEPROM memory cells known in the art are described in U.S. Pat. No. 5,465,231, issued Nov. 7, 1995 in the name of inventor K. Ohsaki and entitled xe2x80x9cEEPROM and Logic LSI Chip Including Such EEPROM,xe2x80x9d U.S. Pat. No. 6,191,980, issued Feb. 20, 2001 in the name of inventors P. J. Kelley et al. and entitled xe2x80x9cSingle-Poly Non-Volatile Memory Cell Having Low-Capacitance Erase Gate,xe2x80x9d R. J. McPartland et al., xe2x80x9cSRAM Embedded Memory with Low Cost, FLASH EEPROM-Switch-Controlled Redundancy,xe2x80x9d Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, Fla., May 21-24, 2000, pp.287-289, and R. J. McPartland and R. Singh, xe2x80x9c1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications,xe2x80x9d Proceedings of the 2000 Symposium on VLSI Circuits, Honolulu, Hawaii, Jun. 15-17, 2000, pp. 158-161, all of which are incorporated by reference herein.
FIG. 1 shows a side sectional view of a portion of a conventional single-poly flash EEPROM memory cell 100 of a type similar to that described in the above-cited U.S. Pat. No. 5,465,231. A corresponding schematic diagram is shown in FIG. 2. The memory cell 100 as shown includes a control device M1 and a switch device M2. M1 is implemented as a P-type metal oxide semiconductor (PMOS) device, and M2 is implemented as an N-type MOS (NMOS) device. More particularly, the cell 100 includes a P-type substrate 102 coupled to a substrate voltage (VSUB) terminal 103 and having an N-tub 104. The N-tub 104 is also commonly referred to as an N-well. The control device MI is formed within the N-tub 104 using P+ source/drain regions 106, 108 and N+ xe2x80x9ctub tiexe2x80x9d or contact region 110, each coupled to a control gate terminal 111. The switch device M2 includes N+ regions 112 and 114 formed in the substrate 102 and coupled to respective source and drain terminals 113 and 115. The control device MI and switch device M2 share a common polysilicon floating gate 120 designed to retain charge after the cell is written, i.e., programmed.
The memory cell 100 is programmed using a channel hot electron (CHE) programming technique, also known as hot electron injection. This technique involves applying a high gate-to-substrate voltage VGS and a high drain-to-substrate voltage VDS to the respective control gate terminal 111 and drain terminal 115 while setting voltage VS of the source terminal 113 and voltage VSUB of the substrate 102 to 0 volts. Typical values for the programming voltages VGS and VDS are 7 volts and 6.5 volts, respectively, as indicated in the FIG. 2 schematic diagram. The heavy source-to-drain electron conduction resulting from these applied voltages generates hot electrons that jump a gate oxide barrier layer (not shown) and land on the polysilicon floating gate 120. This effectively increases the threshold voltage of the switch device M2, thereby programming the memory cell. More specifically, the potential of the floating gate 120 is lowered by the above-noted hot electron injection such that when the floating gate is coupled to the control gate terminal 111 during a subsequent read operation, the potential of the floating gate will be below the threshold of the switch device M2 and M2 will thereby be non-conductive.
Erasure of a programmed cell involves removing electrons from the floating gate 120 so as to increase the potential of the floating gate and thereby lower the effective threshold voltage of the switch device M2. This may involve raising the drain-to-substrate voltage VDS applied to drain terminal 115 to a value near the drain-to-substrate junction breakdown voltage, so as to generate hot holes that are swept, via the drain-to-gate electric field, through the above-noted oxide barrier layer to the floating gate 120. This is equivalent to removing electrons from the floating gate. The object of this erase operation is to raise the potential of the floating gate 120 such that when the floating gate is coupled to the control gate terminal 111 during a subsequent read operation, the potential of the floating gate will be above the threshold of the switch device M2 and M2 will thereby be conductive.
A typical conventional EEPROM or other memory device will generally be configured as an array of memory cells arranged in rows and columns. In an array of cells of the type described in conjunction with FIGS. 1 and 2 above, the above-noted typical VDS programming voltage of 6.5 volts is simultaneously applied to the drain terminals of multiple columns of cells, but the cells are programmed only a single selected row at time by raising the control gate voltage VGS of the selected row to the typical programming voltage of 7 volts. Cells in the non-selected rows see the high drain voltage VDS but not the high control gate voltage VGS, and should not be programmed or erased.
Although such an arrangement may be acceptable in certain older generations of CMOS technologies, the lower drain-to-substrate junction breakdown voltages associated with the more aggressive modem CMOS technologies can lead to significant problems in terms of undesired erasure, also referred to herein as xe2x80x9cprogram disturb.xe2x80x9d For example, the high drain voltage VDS applied to multiple columns of the memory cell array is sufficiently close to the approximately 7 volt drain-to-substrate breakdown voltage associated with modem CMOS technologies that hot holes may be inadvertently generated in the cells of non-selected rows and information thereby erased from those cells. This undesired hot hole erasure can also damage the oxide barrier layer, resulting in a degradation in the ability of the cells to retain programmed information, also referred to herein as their information retention or endurance. The higher programming voltages required also unduly increase the power consumption of the devices.
As is apparent from the foregoing, a need exists in the art for a non-volatile memory cell and associated cell array and memory device having a programming mechanism which alleviates the program disturb problem while also improving cell information retention.
The present invention provides an improved non-volatile memory cell and associated cell array and memory device that in an illustrative embodiment can be configured to substantially eliminate the program disturb problem, while also significantly improving information retention and reducing power consumption relative to conventional devices.
In accordance with one aspect of the invention, a non-volatile memory cell is configured so as to utilize a channel initiated secondary electron (CHISEL) injection programming mechanism. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell.
In an illustrative embodiment, the bias voltage may be on the order of approximately xe2x88x922.0 volts. Through application of this bias voltage, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts. This alleviates program disturb problems that can result, e.g., when the drain-to-substrate voltage is applied to multiple columns of an array of cells that are programmed one row at a time, and also prevents the above-noted damage to the oxide barrier layer.
In accordance with another aspect of the invention, the switch device is formed in a first tub region of a first conductivity type, e.g., the same conductivity type as the substrate, and the first tub region is itself formed in a second tub region of a second conductivity type. The contact region formed in the first tub region is of the first conductivity type, and is adapted for application of a voltage to the first tub region during the programming operation of the memory cell. The second tub region may also have a contact region formed therein, with that contact region being adapted for application of a voltage to the second tub region. The latter applied voltage may be on the order of 0 volts or ground potential, such that the junction formed between the first tub region and the second tub region is in a reverse bias state.
In addition to the advantages of reduced program disturb and improved retention, a non-volatile memory device in accordance with the invention can be operated using lower programming voltages than conventional devices, and thus requires less power.
The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications, but can also be used in other applications.